This invention relates to a high-speed serial data transmission system, and more particularly to a serial high-speed data transmission system which uses time-division multiplexing and demultiplexing techniques in which the maximum permissible data transmission rate of the system is not limited by the switching speed or settling time of latches used in the multiplexer and demultiplexer circuits, and which does not require the generation and distribution of a clock signal having a frequency at least as high as half the data transmission rate.
Where a high-bandwidth serial transmission channel is available, it is typical to combine a number of individual lower bandwidth signals for simultaneous transmission over the channel, and to recover the individual signals at the receiving end of the channel. It is known in the art to use a time-division multiplexer to combine the individual signals and a corresponding time-division demultiplexer to recover the individual signals.
A time-division multiplexer is a circuit which provides for the transmission of two or more input signals over a common serial output data path by using successive time intervals for sharing the output data path among the input signals. The basic function of the time-division multiplexer is to couple each signal in sequence to the output data path for a predetermined time interval.
A time-division demultiplexer is a circuit which performs the inverse function of recovering from the serial data transmitted over the data path the individual input signal which were combined and serialized by the time-division multiplexer.
In general, the input signals are distinct serial data streams, which are sampled and interleaved by the time-division multiplexer to provide a single serial data stream at a much higher data rate than the input data streams.
New technological developments have created the desirability for time-division multiplexers with ever increasing maximum output data rate. For example, it is desired to have time-division multiplexers which are capable of combining the parallel data words generated by very-high-speed digital processors for transmission on high speed serial data links. Similarly, it is desired to have time-division multiplexers which can generate a multiplexed output data stream of a high enough data rate to exploit the full potential of new high-bandwidth transmission technologies such as fiber optic or superconductor transmission lines.
Various multiplexer circuit configurations are known in the art, including those disclosed in U.S. Pat. No. 4,486,880 to Jeffrey et al., U.S. Pat. No. 4,593,390 to Hildebrand et al., and U.S. Pat. No. 4,686,674 to Lam. These circuit configurations, and others discussed below, have the problem in that the maximum output data rate is limited by the switching and settling time of various sequential devices such as latches. They also have the problem in that a clock signal of a frequency at least as great as half the output data rate must be generated and routed to some of the circuit elements of the multiplexer.
Referring to FIGS. 1A through 1E, a generic representation of a conventional time-division multiplexer and a variety of known time-division multiplexer circuit configurations are shown. In each example four data lines designated D0, Dl, D2, and D3 are shown entering the time-division multiplexer at the left, and a multiplexed output Y is shown leaving the time-division multiplexer at the right.
In FIG. 1A, a simplified generic multiplexer is shown. Selector 10, shown generically as a switch having four positions, equal to the number of inputs, sequentially connects the four input signals D0-D3 to the output Y in a cyclic fashion. If each of the inputs has a data rate characterized by a period T, the selector may cycle through the four switch positions in the period T, selecting each of the inputs for an interval of duration T/4. The output signal, under these circumstances, has a data rate characterized by a period of T/4.
In FIG. 1B, four D-type flip-flops and three 2-to-1 multiplexers are cascaded to multiplex four data streams D0-D3 into one data stream at the output Y. At the moment when the data value present at output Y is a data value of D0, the 2-1 multiplexer 11 is selecting data line D0. After the passage of an interval T/4, the data value present at output Y will be determined by the data value of Dl, which data value has been delayed relative to the data value of D0 by the D-type flip-flop 12. After the passage of another interval T/4, the data value present at output Y will be determined by the data value of D2, which data value has been delayed relative to the data value at D0 by its passage through two D-type flip-flops 13 and 12. In a similar manner the data value of D3 will eventually become the data value at output Y, and the process is repeated for four more values of D0 through D3.
FIG. 1C shows another known time-division multiplexer circuit 101. Data lines D0 through D3 are respectively provided to AND gates 14. Pulse generator 15 generates gating signals .phi.1 through .phi.4 related as shown in the timing diagram 102 of the figure. Each gating signal .phi.1-.phi.4 has a duty cycle of nominal 25%, such that at a given instant only one of the four gating signals .phi.1-.phi.4 is high. If the data rate at the inputs is characterized by a period T, a given gating signal .phi. is high for a duration of T/4. For example, during the time that .phi.1 is high, the data value of D0 determines the data value at output Y. Gating signal .phi.2 goes high as .phi.1 goes low, and the value of Dl becomes the data value at output Y, and so on through the input lines.
FIG. 1D shows a known time-division multiplexer circuit configuration 103 having a timed tree structure. Counter 16 generates control signals so that each of 2-1 multiplexers 17 selects one of its two inputs, and the 2-1 multiplexer 18 selects one of its two inputs, which are the outputs of the multiplexers 17.
Each of these time-division multiplexer circuit configurations of FIGS. 1B-1D has the drawbacks mentioned above. In the time-division multiplexer of FIG. 1B, for example, a clock signal CLK with a period of T/4 must be generated and distributed to at least four circuit elements. This clock signal, with a frequency corresponding to the output data rate, imposes severe design and layout constraints as the output data rate is increased. Additionally, each D-type flip-flop, including flip-flops 12 and 13, and each 2-1 multiplexer, including multiplexer 11, has to be fast enough to switch and settle within the period of the CLK signal. Depending on the output data rate required, sufficiently fast flip-flops and multiplexers may be expensive or unavailable.
In the time-division multiplexer of FIG. 1C, the pulse generator 15 has to generate the multiplexer control signals .phi.1-.phi.4, each of which must rise and fall in period T/4. The circuit path carrying each of the multiplexer control signals .phi.1-.phi.4 is subject to severe design and layout constraints. Not only must the circuit elements in the pulse generator 15 switch and settle faster than time T/4, but the gates 14 must also switch and settle that quickly. As in the previous example, the maximum output data rate achievable is limited by the speeds of the flip-flops of the pulse generator 15 and the gates 14 and 106 making up the selector circuit.
In the time-division multiplexer of FIG. 1D, the maximum output data rate achievable by the whole circuit is limited by the maximum clock rate of the counter 16 and the maximum switching speed of the 2-1 multiplexer 18. As in the previous examples, at least one of the multiplexer control signals, in this case the signal 19 controlling multiplexer 18, necessarily has a frequency as high as that of the output data. In some instances, the clock signal CLK itself may be used as the control signal 19 applied to the multiplexer 18 to allow a reduction in the frequency of clock signal CLK by a factor of two. However, the problems of generating and distributing such a high-frequency signal may impose a practical limit on the maximum output data rate of the multiplexer 103.
Where the maximum output data rate of a particular time-division multiplexer is limited by the switching and settling time of circuit elements used in the time-division multiplexer, one way to increase such output data rate is by employing faster circuit elements. For example, improvements may be achieved by using gallium arsenide technology instead of conventional silicon technology, or by using bipolar rather than MOS circuit elements. However, even with the fastest semiconductor technologies, known time-division multiplexer circuit configurations may not be fast enough to fully exploit the advances in data transmission line technology.
At the receiving end of the serial data channel, it is necessary to demultiplex the data to recover the original input signals that were combined by the multiplexer. Where the signals were combined by a conventional time-division multiplexer, the demultiplexing may be performed, for example, by a circuit such as that shown in FIG. 1E.
Referring now to FIG. 1E, the incoming serial data at input Y is supplied to the input of the first stage of a four stage shift register formed by four D-type flip-flops 14'. Each of the D-type flip-flops 14' of the demultiplexer 104 receives a common high-speed clock signal .phi., which may be derived from the incoming serial data stream at input Y or received from the source of the incoming data. Successive data values of the incoming serial data stream at the input Y are latched by the first stage and progressively shifted to subsequent stages of the shift register each time the clock signal .phi. goes high. In this way each of the data values of the input signals D0-D3 which were combined by the multiplexer are made available at the outputs of corresponding flip-flops 14'.
However, the same drawbacks of known multiplexer circuit configurations discussed above are also present in known time-division demultiplexer circuits. So a data transmission system composed of known multiplexer and demultiplexer circuits suffers from the disadvantage of these drawbacks.
Thus, there clearly is a need for a time-division multiplexed data transmission system that avoids the limitations imposed by slow switching and settling times of latches and other logical components, and avoids the problem of having to generate and distribute a clock signal of a frequency as great as the output data rate of the multiplexer.